1. Field of the Invention
The embodiments of the invention generally relate to processes for manufacturing integrated circuit devices and, more specifically, to various methods that eliminate openings within substrates that can be formed below mask process control marks.
2. Description of the Related Art
When manufacturing integrated circuit devices, it is common to utilize masks that include process control marks that ensure that the mask is in the proper position relative to the substrate. For example, through silicon vias (TSV's) are used for conductively contacting the backside of a ground wafer. Uses of TSV's include grounded emitter SiGe, insulated TSV silicon carriers, etc. For the insulated TSV approach, the TSV is patterned, etched, and filled with a placeholder polysilicon, which is later removed and refilled with a conductor, such as tungsten. This disclosure describes the lithographic marks used for aligning, measuring overlay, and measuring critical dimensions used with integrated circuit technologies, such as insulated and grounded TSV's and other structures.
With insulated TSV's, a TSV opening is patterned and etched prior to deep trench capacitor and/or shallow trench isolation formation. With grounded TSV's, a TSV opening is patterned and etched post transistor formation in the contact module. Problems with the formation of such structures include that extra structures are placed by the mask house somewhat randomly for their mask metrology (critical dimension (cd), cd variability, etc.). If these extra shapes intersect an N-well-P-well boundary, or if they are inside the wrong well, then the extra shapes may cause a high resistance short path which will degrade yield or reliability.
An etching mask is used to etch out the sacrificial polysilicon from the TSV. The placeholder material removal process is performed with a mixture of isotropic (wet) and anisotropic (dry) etching. If the etching mask shape falls over crystalline silicon, then large cavities will be etched into the silicon. Such cavities can destroy underlying structures. Such extra structures can also exacerbate wafer breakage issues due to alignment of the TSV with the crystal plane.